1. Field of the Invention
The present invention reltes to an etching method and an etching apparatus.
2. Description of the Related Art
In the manufacture of semiconductor ICs, an etching apparatus, an ion implantation apparatus or a sputtering apparatus is conventionally used. In these apparatuses, a semiconductor wafer is fixed on a mounting table in vacuum and processing such as thin film formation or micropattern high-precision formation is performed.
In the above processing, a semiconductor wafer is heated to a high temperature and its physical characteristics change. Therefore, in order to prevent this phenomenon, Japanese Patent Disclosure (Kokai) No. 61-206225, Japanese Utility Model Publication No. 58-41722, Japanese Patent Disclosure (Kokai) No. 60-5540, Japanese Patent Publication No. 62-57066 and the like disclose techniques in which a semiconductor wafer is fixed on a projecting mounting surface of a mounting table by a forced clamp, electrostatic chucking or the like to perform cooling.
In the technique disclosed in Japanese Patent Disclosure (Kokai) No. 61-206225, however, a semiconductor wafer is electrostatically chucked on a mounting table, and a voltage is applied to both the mounting table counter electrode and the mounting table. For this reason, in bias sputtering, desired processing can be performed only when a voltage suited to the processing coincides with that required for electrostatic chucking. In sputtering or etching of another system, desired processing conditions cannot be set. In ion implantation, ion implantation amount measurement is adversely affected. Also, in a mechanism in which a semiconductor wafer is held in contact with an electrode, an electrically conductive member such as a metal must be used as a predetermined member because rigidity is necessary. Electric charges or ions in a plasma gas, however, reach the electrically conductive member around the electrodes to diffuse the plasma. For this reason, the plasma gas cannot be concentrated between the opposed electrodes. As a result, an etching rate is reduced, and etching cannot be uniformly performed.
In the technique disclosed in Japanese Utility Model Publication No. 58-41722, a semiconductor wafer cannot be held in contact with a mounting table throughout its entire surface. For this reason, since processing conditions at portions at which the semiconductor wafer is in contact with the mounting table differ from those at the other portion, processing uniformity is degraded.
In the techniques disclosed in Japanese Patent Disclosure (Kokai) No. 60-5540 and Japanese Patent Publication No. 62-57066, a layer made of a soft and thermal conductive material such as silicone rubber is formed on a projecting mounting surface of a mounting table. The silicone rubber or the like, however, generates dust to contaminate a semiconductor wafer. In addition, a gas or dust generated from inside the silicone rubber or the like reduces a vacuum degree. As a result, processing capacity is reduced to degrade a processing efficiency.
A semiconductor wafer can be reliably held by a ring-like clamp mechanism as disclosed in Japanese Patent Disclosure Nos. 61-212023, 62-105347 and 60-130633. However, if the semiconductor wafer is not clamped by a predetermined urging pressure, its entire rear surface is not uniformly brought into contact with the electrode surface. For this reason, the semiconductor wafer cannot be uniformly etched. Therefore, a peripheral portion of the semiconductor wafer is clamped toward the electrode so that substantially the entire rear surface of the semiconductor wafer is brought into contact with the electrode. In this case, if a clamp pressure is reduced lower than a predetermined pressure, the peripheral portion of the semiconductor wafer is not brought into contact with the electrode but is floated. In contrast, if the clamp pressure is increased higher than the predetermined pressure, the central portion of the semiconductor wafer is floated from the electrode. In either case, a nonetched portion is produced on the semiconductor wafer. In other words, a variation in clamp pressure poses a problem of an etching failure of the semiconductor wafer.
Japanese Patent Disclosure (Kokai) No. 59-94422 discloses a technique in which an upper electrode or a lower electrode on which a semiconductor wafer is mounted is moved vertically if necessary to perform etching of the semiconductor wafer. However, if an interval between the upper and lower electrodes is changed during etching, an etching rate may be largely changed by an electrode interval change. Therefore, an interval between the upper and lower electrodes must be set with very high precision throughout the entire surfaces of both the electrodes. Furthermore, in a structure in which upper and lower electrodes are fixed but an interval between the electrodes largely affects an etching rate of a semiconductor wafer, etching cannot be performed with high precision, high reproducibility, and high yield.
Some etching apparatuses adopt an anodized aluminum electrode capable of stably performing discharge even at a high temperature. The anodized aluminum electrode, however, is gradually consumed as aluminum chloride during etching. For this reason, the electrode has a short service life and therefore must be frequently replaced. As a result, yield of etching is poor, and an etching state must be checked by observing a semiconductor wafer after etching. Therefore, etching cannot be automatically performed.
In addition, the anodized aluminum electrode has an alumina insulating layer of a thickness of 15 to 70 .mu.m on its surface. The alumina layer is used as a dielectric protection film. The alumina insulating layer has, however, a porous structure. For this reason, a large number of small gaps are present in a contact portion between the semiconductor wafer and the alumina insulating layer. As a result, an impedance largely varies between the semiconductor wafer and the anodized aluminum electrode. Therefore, the alumina insulating layer is easily destroyed during etching. If the alumina insulating layer is destroyed, a damage is given to the semiconductor wafer.